ParthusCeva Announces Architecture Standard for Hybrid DSP/RISC-Based System-on-Chip for ARM Environment

San Jose, Calif - September 29, 2003 - ParthusCeva, Inc.,
[(Nasdaq: PCVA); (LSE: PCV)], the industry's leading licensor of Digital
Signal Processor (DSP) cores and solutions today announced a specification
for an architecture covering the integration of ARM cores together with
ParthusCeva DSP SmartCores™.

The majority of System-on-Chips (SoC) combine a RISC microprocessor and
DSP processor core in the same chip creating a complex design, development
and verification process. To reduce the risk, cost and complexity of these
systems, ParthusCeva and ARM, the world's leading developers of DSP
processors and RISC microprocessors respectively, have collaborated in
four key technical areas.

The joint specification standard for hybrid RISC/DSP based
system-on-chip which covers the hardware interfaces between the cores
for sophisticated mailbox-based command and control messaging and bulk
data passing, debug and trace interfaces and protocols for multi-core
debug and software APIs for inter-processor communications. The
specification also includes circuitry for low latency message passing
and bulk data transfer integrated with powerful DMA capabilities.

In support of the architecture, ParthusCeva's announces that
its XpertDSP platform supports AMBA™ methodology.

The development of the RealView® Developer Suite advanced
multi-core debug tools enabling support for ParthusCeva Teak DSP core
and XpertTeak System.

Combined development board environments. ParthusCeva TeakLite
and Teak cores and the XpertDSP sub-system available as core modules
which seamlessly combine with the ARM RealView Integrator™ platform.

"Hybrid solutions combining CPU and DSP cores are key to many new
digital devices and particularly key to the burgeoning
application-processing market," said Gideon Wertheizer, Executive VP of
ParthusCeva. "Our mutual customers will greatly benefit from a standard
integration between the two leading RISC and DSP architectures, and this
further enhances our position as the leading DSP architecture of choice
for the mobile world."

"As a significant number of ARM core-based systems combine an ARM core
and ParthusCeva's DSP cores, ARM's DSP Interface Specification will be of
great value to our mutual customers and should further enhance the
capabilities of the ARM architecture," said Matthew Byatt, Marketing
manager, ARM.

The new specification eases dual core development by combining ASIC
hardware platforms, various development boards, the RealView Debugger and
hardware development tools. In addition, the new standard's installed
software base further enables developers to shorten time to market for
their multi-core chipsets.

The RISC/DSP architecture standard will span the various generations of
ARM processors, including the ARM7™ and ARM9™ core families, alongside all
members of ParthusCeva's industry leading SmartCores DSP family.

About ParthusCeva, Inc.

Further information about ParthusCeva

A PDF copy of this press release is also available here


OakDSPcore, TeakLIte, and Teak are registered
trademarks and XpertTeak and SmartCores are trademarks of ParthusCeva,
Inc. Other brands and products referenced herein are the trademarks or
registered trademarks of their respective holders. ARM and RealView are
registered trademarks of ARM Limited. ARM7, ARM9, and AMBA are trademarks
of ARM Limited. All other brands or product names are the property of
their respective holders. "ARM" is used to represent ARM Holdings plc
(LSE: ARM and Nasdaq: ARMHY); its operating company ARM Limited; and the
regional subsidiaries ARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM
France SAS; ARM Consulting (Shanghai) Co. Ltd.; and ARM Belgium N.V.

ParthusCeva Safe Harbor Statement

Various statements in this press release concerning
ParthusCeva's future expectations, plans and prospects are
"forward-looking statements", which are subject to certain risks and
uncertainties that could cause actual results to differ materially from
those stated. Any statements that are not statements of historical fact
(including, without limitation, statements to the effect that the company
or its management "believes", "expects", "anticipates", "plans" and
similar expressions) should be considered forward-looking statements.
These statements are subject to a number of risks and uncertainties that
could cause actual results to differ materially from those described,
including the following:

  • the industries in which we license our
    technology are experiencing a challenging period of slow growth that has
    negatively impacted and could continue to negatively impact our business
    and operating results;

  • the markets in which we operate are highly
    competitive, and as a result we could experience a loss of sales, lower
    prices and lower revenue;

  • our operating results fluctuate from quarter to
    quarter due to a variety of factors including our lengthy sales cycle,
    and are not a meaningful indicator for future performance

  • we rely significantly on revenue derived from a
    limited number of licensees; and

  • other risks discussed in "Management's
    Discussion and Analysis of Financial Condition and Results of
    Operations--Factors that Could Affect Our Operating Results," in our
    quarterly report on Form 10-Q for the first quarter of 2003, filed with
    the U.S. Securities and Exchange Commission on May 14, 2003.