Description
About the Business Unit:
The AI Division is a unique and dedicated group within Ceva, driving innovation in Machine Learning and Generative AI architectures for edge devices and cloud inference. Our R&D domains span Neural Network Processors (NPU), Vision DSPs, and advanced AI algorithms for applications across smartphones, tablets, automotive, surveillance cameras and many more edge AI systems.
We combine cutting-edge hardware IP design with embedded software and system-level solutions, enabling the next generation of intelligent and energy-efficient devices.
About the Role:
As a Digital Verification Engineer, you will work on a full state of the art verification flow from architecture definition, through verification strategy, environment micro-ARCH, test plan, functional coverage plan and up to advanced verification sign off process
Responsibilities:
You will directly contribute to the verification of our fully integrated solutions, design in System Verilog new verification environment checker and test bench, being a major contributor to the verification process, and improve performance and quality. An empty job that is used for creating requisitions 'from scratch'
Requirements
- B.Sc /M.Sc. graduates in Electrical Engineering from a leading University.
- 5+ years of experience in Verification.
- Knowledge of SV-UVM.
- Self-motivated and self-directed, proactive.
- Ability to achieve results in a fast moving, agile flow and dynamic environment, both locally and across the organization.
- Ability to troubleshoot and analyze complex problems.
- Great communication skills.
- Fluent English.
- Team player.