Description
About the Business Unit:
CEVA is at the forefront of developing next-generation cellular communication systems. We are building the next generation communication infrastructure of 5G modems for User Equipment (UE) and base stations. Among other applications, we are also focusing on space and satellite infrastructure.
About the Role:
As a Senior VLSI Designer, you’ll lead the full design flow of advanced DSP cores and accelerators—from architecture to timing closure. This hands-on role is key to developing the IP’s behind the next-generation products, with strong cross-functional collaboration and technical ownership.
Responsibilities:
As a Senior VLSI Designer, you will be responsible for the end-to-end design and implementation of advanced digital IPs, including DSP cores and hardware accelerators. You will work across the full design flow—from architecture definition and micro-architecture design, through RTL development and verification, to synthesis, timing closure, and static timing analysis (STA). Your work will directly contribute to the silicon success of next-generation products across various domains.
Requirements
- B.Sc. / M.Sc. in Electrical Engineering from a leading institute
- 5+ years of experience in VLSI design.
- Proficiency in RTL design (Verilog/System Verilog), synthesis, and timing analysis.
- Familiarity with EDA tools (Synopsys, Cadence, Mentor).
- Strong understanding of digital design principles, SoC architecture, and low-power techniques.
- Excellent problem-solving and communication skills.
- Fluent English (Oral and written)
Advantages:
- Knowledge of signal processing and digital communication systems.
- Experience in scripting using TCL and Python