The technology world is a fast changing world. With fast-paced technical advances and new and attractive market opportunities opening up all the time, there are a few things that do remain constant. These things are, the drive for faster time to market and higher productivity, leading to better profitability for a product company. Over the years, chip design complexity has grown in leaps and bounds. And most chip-based products need software running on them to make them useful. When a product is launched, both the hardware and the software need to be ready. This requires the software to have been developed, tested and ready to go when the hardware is ready for shipment. Thus, software development needs to start almost at the same time as the hardware development begins. To make things more challenging, portions of a hardware system may get defined and/or modified over the course of development. Consequently, hardware/software co-development and co-verification has become a corner stone of product development. As a result, integration of software with hardware has to happen well before chips and boards become available.
To accommodate and address these challenges, productivity methodologies, tools and platforms are regularly being brought to market to reduce risk and development time. One such platform is the virtual simulation platform.
Virtual Simulation Platform and SystemC Simulator
A virtual simulation platform represents various components of the hardware system in software form, so software development could progress until corresponding hardware become available. As a programming language, SystemC can be used to specify hardware and software descriptions as abstract behavioral models. SystemC also provides an event-driven simulation interface through which a developer can simulate concurrent processes. An executable model of a full system can be generated for SoC simulations even with portions of the system not yet having been designed. In essence, a typical virtual simulation platform is a SystemC based simulator.
Value of a Virtual Platform Simulator (VPS)
A VPS makes software development possible ahead of silicon, FPGA prototype or even RTL simulation. On the one hand, developing software on the actual hardware is better. On the other hand, using virtual hardware does provide some benefits. The virtual hardware can be controlled and monitored better for software development purposes. A VPS offers full visibility into any part of the system and also makes it possible to recreate error conditions that may be difficult to repeat with actual hardware. The virtual platform also enhances interactions and communications among hardware and software team members. All in all, a VPS makes hardware verification, software development, debugging and hardware/software integration more efficient and streamlined.
CEVA’s SoC Simulator
CEVA’s SoC simulator offers an integrated System-C simulation environment that allows system engineers, architects and software developers to model, profile and debug at pre-silicon stage. The virtual simulator can be used for architecture definition and fast prototyping and serves as an effective IP evaluation and proof of concept (PoC) tool. The simulator supports all CEVA IP cores including vector and scalar DSP cores and hardware accelerators. It seamlessly interfaces with MATLAB for developing algorithms and tests. CEVA customers can emulate their system on a FPGA platform for final verification.
Salient Features
- Includes a GUI for visualization and configuration of SoC connectivity for AXI, APB and Direct connections
- Provides AXI and APB Masters and Slaves transaction logs
- Connects to processor debugger via API, allowing stepping through the source code for debugging
- Allows easy addition of new hardware module through a few lines of SystemC code and definition in the configuration file and main SystemC top section
- Allows newly added modules to connect to AXI/APB and CEVA cores and access shared memory
PentaG-RAN and SystemC Simulator
5G designs are very complex, involving a number of specialized components, including 5G PHY chains, 5G software modules, drivers, DSP cores, libraries, RTOS, etc., To accelerate adoption, CEVA recently announced its PentaG-RAN offering, the industry’s first baseband platform IP for 5G RAN ASICs, targeting the 5G infrastructure market. The PentaG-RAN platform architecture offers a complete solution that delivers up to 10X savings in power and area compared to FPGA and COTS CPU based alternative solutions. It also offers opportunities for customization through incorporation of customers’ proprietary IP to be mixed and matched with a wide range of CEVA accelerators.
PentaG-RAN licensees can further speed up time-to-market with CEVA’s VPS which includes reference software for main processing chains and beamforming use cases.
Summary
As covered in this article, virtual platform simulation is very useful and needed for accelerating 5G chip development. CEVA’s SystemC simulator can be used as a virtual platform simulator not only for 5G chip development but for any SoC development that incorporates CEVA DSPs and hardware accelerators. CEVA customers get access to the SoC simulator along with the IDE. Together, the various CEVA PentaG platform IPs and the Virtual Platform Simulator make it easy and efficient to get products to market quickly.
You can explore how you could benefit from CEVA’s solutions for various segments here.
Tal Dekel